MathWorks is launching a HDL Coder, which automatically generates HDL code from MATLAB, allowing engineers to implement FPGA and ASIC designs from MATLAB. MathWorks is also unveiling a HDL Verifier, which includes FPGA hardware-in-the-loop capabilities for testing FPGA and ASIC designs. With these two products, MathWorks now provides HDL code generation and verification across MATLAB and Simulink.
Tom Erkkinen (Manager, Embedded Applications and Certification, MathWorks): With HDL Coder and HDL Verifier, users no longer have to manually write HDL code or test benches to develop FPGA and ASIC designs.
HDL Coder generates portable, synthesizable VHDL and Verilog code from MATLAB functions and Simulink models that can be used for FPGA programming or ASIC prototyping and design. Traceability between Simulink models and generated HDL code also supports the development of applications that adhere to DO-254 and other standards. HDL Coder also offers integration with Xilinx ISE design suite.
HDL Verifier supports FPGA hardware-in-the-loop verification for Altera and Xilinx FPGA boards. HDL Verifier provides co-simulation interfaces that link MATLAB and Simulink with Cadence Incisive, Mentor Graphics ModelSim, and Questa HDL simulators.
HDL Coder and HDL Verifier are available immediately. Prices for HDL Coder start at $10,000, and for HDL Verifier start at $3,250.